1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to isolating back gates for fully depleted semiconductor-on-insulator devices.
2. Background Art
Doped well regions in the substrate silicon of a semiconductor-on-insulator (SOI) wafer can be used as back gates for fully depleted (FDSOI) transistors. In typical CMOS circuitry, the close proximity of PFETs to NFETs make it very difficult to independently gate both types of FETs since the wells will either merge and short circuit, or a common gate (p-type) with a separate n-well gate must be used. In the first instance, a large density penalty must be paid, in the second, all (of one type) gates must be globally connected, prohibiting many circuit applications.